cy24204 mediaclock? dtv, stb clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07450 rev. *d revised may 22, 2008 features integrated phase-locked loop (pll) low jitter, high-accuracy outputs vcxo with analog adjust 3.3v operation benefits internal pll with up to 400-mhz internal operation meets critical timing requirem ents in complex system designs large 150-ppm range, better linearity enables application compatibility part number outputs input frequency output frequency range cy24204-3 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mhz (frequency selectable) cy24204-4 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mh z (frequency selectable, increased vcxo pull range) cy24204-5 4 27-mhz crystal input two copies of 27-mhz reference clock output, two copies of 27/27.027/74.250/74.17582418 mh z (frequency selectable, increased output drive strength) xin xout output multiplexer and dividers pll osc. clk1 q p vco vddl avss avdd vss fs0 fs1 clk2 refclk1 vssl vdd oe vcxo refclk2 (-3,-4,-5) logic block diagram [+] feedback
cy24204 document #: 38-07450 rev. *d page 2 of 7 pin configuration figure 1. cy24204-3,4,5 16-pin tssop table 1. pin definition name pin number description xin 1 reference crystal input. v dd 2 voltage supply. av dd 3 analog voltage supply. vcxo 4 input analog control for vcxo. av ss 5 analog ground. v ssl 6 clk ground. refclk2 7 reference clock output. refclk1 8 reference clock output. clk1 9 27/27.027/74.250/74.17582418-mhz clock output (frequency selectable). fs0 10 frequency select 0, weak internal pull up. v ddl 11 clk voltage supply. clk2 12 27/27.027/74.250/74.17582418-mhz clock output (frequency selectable). v ss 13 ground. fs1 14 frequency select 1, weak internal pull up. oe 15 output enable, weak internal pull up. xout 16 reference crystal output. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 vss vssl fs0 xin xout vdd vcxo avss refclk1 oe fs1 avdd vddl clk2 clk1 refclk2 24204-,3,4,5 frequency select options oe fs1 fs0 clk1/clk2 [1] refclk 1/2 unit 000 off 27 mhz 001 off 27 mhz 010 off 27 mhz 011 off 27 mhz 100 27 27 mhz 1 0 1 27.027 27 mhz 1 1 0 74.250 27 mhz 1 1 1 74.17582418 27 mhz note 1. ?off? = output is driven high. [+] feedback
cy24204 document #: 38-07450 rev. *d page 3 of 7 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. supply voltage (v dd , av ddl , v ddl ) ................. ?0.5 to +7.0v dc input voltage ......................................?0.5v to v dd + 0.5 storage temperature (non-condensing).... ?55 c to +125 c junction temperature ................................. ?40 c to +125 c data retention at tj=125 c ..................................> 10 years package power dissipation...................................... 350 mw esd (human body model) mil- std-883......... ........... 2000v pullable crystal specifications parameter description comments min typ. max unit f nom nominal crystal frequency parallel resonance, fundamental mode, at cut ?27.0?mhz c lnom nominal load capacitance ? 14 ? pf r 1 equivalent series resistance (esr) fundamental mode ? 25 r 3 /r 1 ratio of third overtone mode esr to fundamental mode esr ratio used because typical r 1 values are much less than the maximum spec 3?? dl crystal drive level no external series resistor assumed ? 0.5 2 mw f 3sephi third overtone separation from 3*f nom high side 300 ? ? ppm f 3seplo third overtone separation from 3*f nom low side ? ? ?150 ppm c 0 crystal shunt capacitance ? ? 7 pf c 0 /c 1 ratio of shunt to motional capacitance 180 ? 250 c 1 crystal motional capacitance 14.4 18 21.6 ff recommended oper ating conditions parameter description min typ. max unit v dd /av ddl /v ddl operating voltage 3.135 3.3 3.465 v t a ambient temperature 0 ? 70 c c load max. load capacitance ? ? 15 pf t pu power up time for all v dd s to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms dc electrical specifications parameter [1] name description min typ. max unit i oh1 output high current for -3,-4, v oh = v dd ? 0.5, v dd /v ddl = 3.3v 12 24 ? ma i ol1 output low current for -3,-4 v ol = 0.5, v dd /v ddl = 3.3v 12 24 ? ma i oh2 output high current for -5 v oh = v dd ? 0.5, v dd /v ddl = 3.3v 18 26 ? ma i ol2 output low current for -5 v ol = 0.5, v dd /v ddl = 3.3v 18 26 ? ma v ih input high voltage cmos levels, 70% of v dd 0.7 ? ? v dd v il input low voltage cmos levels, 30% of v dd ??0.3v dd i vdd supply current av dd /v dd current ? ? 25 ma i vddl supply current v ddl current (v ddl = 3.47v) ? ? 20 ma c in input capacitance ? ? 7 pf note 1. not 100% tested. [+] feedback
cy24204 document #: 38-07450 rev. *d page 4 of 7 figure 2. test and measurement setup voltage and timing definitions f xo v cxo pullability range nominal pullability for -3,-5 150 ? ? ppm f xo v cxo pullability range extended pullability for -4 ? 200 ? ppm v vcxo v cxo input range 0 ? v dd v r up pull up resistor on inputs v dd = 3.14 to 3.47v, measured at v in = 0v ? 100 150 k dc electrical specifi cations (continued) parameter [1] name description min typ. max unit ac electrical specifications parameter [1] name description min typ. max unit dc output duty cycle duty cycle is defined in figure 3 ; t1/t2, 50% of v dd 45 50 55 % er 1 rising edge rate for -3,-4 output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf see figure 4 . 0.8 1.4 ? v/ns ef 1 falling edge rate for -3,-4 output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf see figure 4 . 0.8 1.4 ? v/ns er 2 rising edge rate for -5 output clock edge rate, measured from 20% to 80% of v dd , c load = 15 pf see figure 4 . 1.0 1.8 ? v/ns ef 2 falling edge rate for -5 output clock edge rate, measured from 80% to 20% of v dd , c load = 15 pf see figure 4 . 1.0 1.8 ? v/ns t 9 clock jitter clk1, clk2 peak-peak period jitter ? 120 ? ps t 10 pll lock time ? ? 3 ms 0.1 f v dds outputs c load gnd dut clock output v dd 50% of v dd 0v t 1 t 2 figure 3. duty cycle definition [+] feedback
cy24204 document #: 38-07450 rev. *d page 5 of 7 clock output t 3 t 4 v dd 80% of v dd 20% of v dd 0v figure 4. er = (0.6 x v dd ) /t3, ef = (0.6 x v dd ) /t4 ordering information ordering code package name package type operating range operating voltage pb-free CY24204ZXC-3 [2] zz16 16-pin tssop commercial 3.3v CY24204ZXC-3t [2] zz16 16-pin tssop-tape and reel commercial 3.3v cy24204zxc-4 [2] zz16 16-pin tssop commercial 3.3v cy24204zxc-4t [2] zz16 16-pin tssop-tape and reel commercial 3.3v cy24204zxc-5 [2] zz16 16-pin tssop commercial 3.3v cy24204zxc-5t [2] zz16 16-pin tssop-tape and reel commercial 3.3v cy24204kzxc-3 zz16 16-pin tssop commercial 3.3v cy24204kzxc-3t zz16 16-pin tssop-tape and reel commercial 3.3v note 2. not recommended for new designs. [+] feedback
cy24204 document #: 38-07450 rev. *d page 6 of 7 package drawing figure 5. 16-lead tssop 4.40mm body 16.173 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin1id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge dimensions in mm[inches] min. max. reference jedec mo-153 package weight 0.05gms 51-85091-*a [+] feedback
document #: 38-07450 rev. *d revised may 22, 2008 page 7 of 7 mediaclock is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document may be the trademarks of their respective holders. cy24204 ? cypress semiconductor corporation, 2003-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy24204 mediaclock? dtv, stb clock generator document number: 38-07450 rev. ecn no. submission date orig. of change description of change ** 123842 04/10/03 ckn new data sheet *a 128775 09/0803 ija added -4 and -5 parts *b 214080 see ecn rgl added -6 part *c 310573 see ecn rgl removed -1,-2 and -6 parts added lead-free devices for -3, -4, and -5 parts *d 2440886 see ecn kvm/aesa updated template. added note ?not recommended for new designs.? added part number cy24204kzxc-3, and cy24204kzxc-3t in ordering information table. removed non-pb-free part numbers (those beginning cy24204zc). replaced ?lead-free? with ?pb-free?. [+] feedback
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